Interested to Buy Any Domain ? << Click Here >> for more details...
Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
4 14254For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
3 11846Explain the operation considering a two processor computer system with a cache for each processor.
2890Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
1 18338In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
3 21038You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
4 16244
What are the various regions of operation of mosfet? How are those regions used?
Explain how logical gates are controlled by Boolean logic?
What happens if we delay the enabling of Clock signal?
Draw the stick diagram of a NOR gate. Optimize it
What transistor level design tools are you proficient with? What types of designs were they used on?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
What are the steps involved in designing an optimal pad ring?
Differences between Array and Booth Multipliers?
What are the Advantages and disadvantages of Mealy and Moore?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Explain the Various steps in Synthesis?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What are the steps required to solve setup and hold violations in vlsi?
