VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

Insights of a Tri-State Inverter?

Intel,

3 9000

Basic Stuff related to Perl?

Intel,

2822

Have you studied buses? What types?

Intel,

5 16998

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

Intel,

4 14113

How many bit combinations are there in a byte?

Intel,

6 12070

For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

Intel,

3 11713

Explain the operation considering a two processor computer system with a cache for each processor.

Intel,

2852

What are the main issues associated with multiprocessor caches and how might you solve them?

Intel,

1 9858

Explain the difference between write through and write back cache.

Intel,

2 19131

Are you familiar with the term MESI?

Intel,

1 11136

Are you familiar with the term snooping?

Intel,

1 10125

Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

Intel,

1 18245

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

IBM, Intel, nvidia,

3 20857

You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

Intel,

4 16081

What are the total number of lines written by you in C/C++? What compiler was used?

Intel, Zensar,

1 5648

Post New VLSI Questions

Un-Answered Questions { VLSI }

For CMOS logic, give the various techniques you know to minimize power consumption

1410

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3869

Draw the Layout of an Inverter?

2507

Write a program to explain the comparator?

1156

Explain what is the use of defpararm?

1157

Give the cross-sectional diagram of the cmos.

1002

Explain what is the depletion region?

1089

Explain CMOS Inverter transfer characteristics?

3924

What is Body Effect?

2521

What happens if we use an Inverter instead of the Differential Sense Amplifier?

3314

Explain what is slack?

1073

What is the function of chain reordering?

1077

Explain what is scr (silicon controlled rectifier)?

1064

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1204

Give various factors on which threshold voltage depends.

1306

For More Un-Answered { VLSI } Questions Click Here