In what cases do you need to double clock a signal before
presenting it to a synchronous state machine?
Answers were Sorted based on User's Feedback
Answer / amar
this situation basically arises when a signal does clock
domain crossing. to synchronize the clock with the target
domain clock and to avoid metastability issues synchronizers
which are like double clocking are used in designs
| Is This Answer Correct ? | 19 Yes | 1 No |
Answer / prashant patil
if the input signal is asynchronous with the clock (state
machine clock), then you need to double clock the same
signal to synchronize with the state machine clock.
| Is This Answer Correct ? | 21 Yes | 7 No |
Answer / prasanna
When signal transfer from one clock domain sequential to
another clock domain sequential logic
| Is This Answer Correct ? | 13 Yes | 6 No |
Why do we need both PMOS and NMOS transistors to implement a pass gate?
Id vs. Vds Characteristics of NMOS and PMOS transistors?
1 Answers Brillient, Intel, ISRO,
Explain the difference between write through and write back cache.
what are three regions of operation of MOSFET and how are they used?
What happens to delay if you increase load capacitance?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
Mention what are the two types of procedural blocks in Verilog?
How do you detect a sequence of "1101" arriving serially from a signal line?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Describe the various effects of scaling?
Explain Basic Stuff related to Perl?
what is conductance and valence band?