In what cases do you need to double clock a signal before
presenting it to a synchronous state machine?
Answers were Sorted based on User's Feedback
Answer / amar
this situation basically arises when a signal does clock
domain crossing. to synchronize the clock with the target
domain clock and to avoid metastability issues synchronizers
which are like double clocking are used in designs
| Is This Answer Correct ? | 19 Yes | 1 No |
Answer / prashant patil
if the input signal is asynchronous with the clock (state
machine clock), then you need to double clock the same
signal to synchronize with the state machine clock.
| Is This Answer Correct ? | 21 Yes | 7 No |
Answer / prasanna
When signal transfer from one clock domain sequential to
another clock domain sequential logic
| Is This Answer Correct ? | 13 Yes | 6 No |
Mention what are the two types of procedural blocks in Verilog?
what is the use of defpararm?
What types of high speed CMOS circuits have you designed?
Explain the Working of a 2-stage OPAMP?
Draw a CMOS Inverter. Explain its transfer characteristics
Draw the Layout of an Inverter?
What is Fermi level?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
What are the different design constraints occur in the synthesis phase?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What is the build-in potential?
How do you detect if two 8-bit signals are same?