In what cases do you need to double clock a signal before
presenting it to a synchronous state machine?
Answers were Sorted based on User's Feedback
Answer / amar
this situation basically arises when a signal does clock
domain crossing. to synchronize the clock with the target
domain clock and to avoid metastability issues synchronizers
which are like double clocking are used in designs
Is This Answer Correct ? | 19 Yes | 1 No |
Answer / prashant patil
if the input signal is asynchronous with the clock (state
machine clock), then you need to double clock the same
signal to synchronize with the state machine clock.
Is This Answer Correct ? | 21 Yes | 7 No |
Answer / prasanna
When signal transfer from one clock domain sequential to
another clock domain sequential logic
Is This Answer Correct ? | 13 Yes | 6 No |
what is SCR (Silicon Controlled Rectifier)?
6-T XOR gate?
What is interrupt latency?
Have you studied buses? What types?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Differences between blocking and Non-blocking statements in Verilog?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
Explain what is the use of defpararm?
Explain Cross section of a PMOS transistor?
Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
what is short Channel effect.