Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Explain what is slack?
6-T XOR gate?
What is threshold voltage?
What is the function of tie-high and tie-low cells?
What are the steps involved in designing an optimal pad ring?
How can you model a SRAM at RTL Level?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
Draw the stick diagram of a NOR gate. Optimize it
What's the price in 1K quantity?
Explain depletion region.
Explain Cross section of a PMOS transistor?
What does the above code synthesize to?
Give various factors on which threshold voltage depends.
Draw a 6-T SRAM Cell and explain the Read and Write operations