6-T XOR gate?

4184

What types of high speed CMOS circuits have you designed?

2510

why is the number of gate inputs to CMOS gates usually limited to four?

1277

For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

2348

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1154

what is multiplexer?

1097

In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1126

What does it mean “the channel is pinched off”?

1308

What was your role in the silicon evaluation/product ramp? What tools did you use?

3653

Mention what are the two types of procedural blocks in Verilog?

1214

Are you familiar with the term snooping?

3430

what is the use of defpararm?

1099

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3820

What are the different ways in which antenna violation can be prevented?

1070

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

3329