Answer / neto colina

Is a widely used cache coherency and memory coherence
protocol introduced by Intel. Modified Exclusive Shared
Invalid are the protocol States.

M means value has been modified from main memory and the
cache is required to write the data back to main memory,
before permitting any other read of the main memory state.
(ITS DIRTY)

E IS CLEAN: Value Match with main memory

S Cache may be stored in other caches of the machine

I Invalid

Explain the various MOSFET Capacitances & their significance?

1 Answers  

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why is the number of gate inputs to CMOS gates usually limited to four?

0 Answers  

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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How to improve these parameters? (Cascode topology, use long channel transistors)

0 Answers  

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Cross section of a PMOS transistor?

0 Answers   Intel,

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What is charge sharing?

2 Answers   Cypress Semiconductor, Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

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What is the difference between = and == in C?

5 Answers   Intel,

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Mention what are three regions of operation of mosfet and how are they used?

0 Answers  

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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