Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

VLSI Interview Questions
Questions Answers Views Company eMail

What are the Factors affecting Power Consumption on a chip?

Intel,

1227

Explain various adders and difference between them?

Intel,

1152

For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

Intel,

1193

Implement a function with both ratioes and domino logic and merits and demerits of each logic?

Intel,

1148

Explain the working of Insights of a pass gate ?

Intel,

1158

Explain the Working of a 2-stage OPAMP?

Intel,

1143

Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

Infosys,

1058

Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

Infosys,

1309

In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

Infosys,

1126

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

Infosys,

1141

Draw the stick diagram of a NOR gate. Optimize it

Infosys,

1225

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

Infosys,

1154

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

Infosys,

1084

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

Infosys,

1056

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

Infosys,

1090


Post New VLSI Questions

Un-Answered Questions { VLSI }

Cross section of a PMOS transistor?

4720


Explain why is the number of gate inputs to cmos gates usually limited to four?

1452


What are the various regions of operation of mosfet? How are those regions used?

1077


What was your role in the silicon evaluation or product ramp? What tools did you use?

2258


For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1390


What is the critical path in a SRAM?

3107


What is the main function of metastability in vsdl?

1005


What are the Factors affecting Power Consumption on a chip?

1227


Draw a 6-T SRAM Cell and explain the Read and Write operations

1230


Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1397


Explain Basic Stuff related to Perl?

989


Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

1408


Explain what is slack?

1014


What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3209


Draw the Layout of an Inverter?

2442