Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
914Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
1143In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
962Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
983Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
989Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
928
How binary number can give a signal or convert into a digital signal?
what are three regions of operation of MOSFET and how are they used?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What transistor level design tools are you proficient with? What types of designs were they used on?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
What are the Factors affecting Power Consumption on a chip?
Explain how logical gates are controlled by Boolean logic?
Draw a 6-T SRAM Cell and explain the Read and Write operations
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
6-T XOR gate?
Explain what is the use of defpararm?
Explain the Charge Sharing problem while sampling data from a Bus?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Differences between Array and Booth Multipliers?
