Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
1105Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
1367In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
1190Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
1205Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
1200Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
1123Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
1147
How can you construct both PMOS and NMOS on a single substrate?
What is the function of tie-high and tie-low cells?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
What's the price in 1K quantity?
Explain the working of 4-bit Up/down Counter?
What does it mean “the channel is pinched off”?
What is the ideal input and output resistance of a current source?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Describe the various effects of scaling?
what is SCR (Silicon Controlled Rectifier)?
How to improve these parameters? (Cascode topology, use long channel transistors)
Explain why present VLSI circuits use MOSFETs instead of BJTs?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Explain how logical gates are controlled by Boolean logic?