Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
891Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
1127In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
932Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
953Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
967Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
901
What products have you designed which have entered high volume production?
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Why does the present vlsi circuits use mosfets instead of bjts?
Working of a 2-stage OPAMP?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
What is the main function of metastability in vsdl?
Explain how logical gates are controlled by Boolean logic?
Explain the Working of a 2-stage OPAMP?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
what are three regions of operation of MOSFET and how are they used?
Differences between IRSIM and SPICE?
Write a VLSI program that implements a toll booth controller?
Differences between Array and Booth Multipliers?
