Answer / narendra

issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.

possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

---

What are the different design constraints occur in the synthesis phase?

0 Answers  

---

What are set up time & hold time constraints? What do they signify?

3 Answers  

---

Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

---

What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

---

Have you studied buses? What types?

1 Answers   Intel,

---

Write a program to explain the comparator?

0 Answers  

---

what is the doping?

5 Answers  

---

What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

---

Insights of a Tri-State Inverter?

3 Answers   Intel,

---

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

---

Explain Basic Stuff related to Perl?

0 Answers   Intel,

---