Answer / narendra

issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.

possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.

Have you studied buses? What types?

5 Answers   Intel,

---

What is the build-in potential?

1 Answers   Wipro,

---

Write a VLSI program that implements a toll booth controller?

0 Answers   Patni,

---

What is the difference between the mealy and moore state machine?

0 Answers  

---

Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

---

What is clock feed through?

2 Answers   Intel,

---

How do you detect if two 8-bit signals are same?

6 Answers  

---

what is multiplexer?

0 Answers  

---

Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

---

Are you familiar with the term snooping?

1 Answers   Intel,

---

What's the price in 1K quantity?

0 Answers   Wipro,

---

How does a pn junction works?

2 Answers   Wipro,

---