Answer / narendra

issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.

possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.

What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

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Explain CMOS Inverter transfer characteristics?

0 Answers   ADS,

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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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what is the use of defpararm?

0 Answers  

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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

0 Answers   Infosys,

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Explain how binary number can give a signal or convert into a digital signal?

0 Answers  

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Implement a function with both ratioed and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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why is the number of gate inputs to CMOS gates usually limited to four?

0 Answers  

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

0 Answers   Intel,

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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Are you familiar with the term snooping?

0 Answers   Intel,

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What is threshold voltage?

0 Answers  

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