What are the main issues associated with multiprocessor
caches and how might you solve them?
Answer / narendra
issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.
possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.
Is This Answer Correct ? | 10 Yes | 0 No |
Implement a 2 I/P and gate using Tran gates?
Write a program to explain the comparator?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
Explain how binary number can give a signal or convert into a digital signal?
Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
Draw a 6-T SRAM Cell and explain the Read and Write operations
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
Factors affecting Power Consumption on a chip?