Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
6 12475Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
3 11840For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
2137Explain the operation considering a two processor computer system with a cache for each processor.
4511
Draw the Layout of an Inverter?
What are the steps involved in designing an optimal pad ring?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What are the Factors affecting Power Consumption on a chip?
How does Vbe and Ic change with temperature?
What are the different design techniques required to create a layout for digital circuits?
How logical gates are controlled by boolean logic?
Explain what is the depletion region?
What transistor level design tools are you proficient with? What types of designs were they used on?
Explain the working of Insights of a pass gate ?
How can you model a SRAM at RTL Level?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
Why does the present vlsi circuits use mosfets instead of bjts?
Explain the Charge Sharing problem while sampling data from a Bus?
what are three regions of operation of MOSFET and how are they used?
