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VLSI Interview Questions
Questions Answers Views Company eMail

How can you model a SRAM at RTL Level?

1 10950

What are the ways to Optimize the Performance of a Difference Amplifier?

2502

How to find the read failiure probablity in SRAM?

2 7467

What's the price in 1K quantity?

Wipro,

2882

Explain the usage of the shared SPI bus?

1 5720

How do you detect a sequence of "1101" arriving serially from a signal line?

nvidia,

7 20517

Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 14019

What are set up time & hold time constraints? What do they signify?

3 17810

How do you detect if two 8-bit signals are same?

6 13710

What is interrupt latency?

3 11962

Have you studied buses? What types?

Intel,

1 5280

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

Intel,

3 12634

For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

Intel,

2447

Explain the operation considering a two processor computer system with a cache for each processor.

Intel,

4773

What are the main issues associated with multiprocessor caches and how might you solve them?

Intel,

2294


Post New VLSI Questions

Un-Answered Questions { VLSI }

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

4171


Give the cross-sectional diagram of the cmos.

1038


Explain CMOS Inverter transfer characteristics?

3963


Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1158


Explain how Verilog is different to normal programming language?

1364


What is Noise Margin? Explain the procedure to determine Noise Margin?

2509


Explain what is Verilog?

1155


Explain what is the depletion region?

1129


Draw a CMOS Inverter. Explain its transfer characteristics

1231


Explain Cross section of an NMOS transistor?

1071


Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

5326


What does it mean “the channel is pinched off”?

1399


Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2887


What was your role in the silicon evaluation or product ramp? What tools did you use?

2382


What are the different ways in which antenna violation can be prevented?

1181