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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
6 13802Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
3 12499For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
2393Explain the operation considering a two processor computer system with a cache for each processor.
4731
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
How about voltage source?
Mention what are the different gates where Boolean logic are applicable?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain depletion region.
What are the steps required to solve setup and hold violations in vlsi?
Explain why is the number of gate inputs to cmos gates usually limited to four?
Explain Basic Stuff related to Perl?
Basic Stuff related to Perl?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Explain the working of Insights of a pass gate ?
What types of CMOS memories have you designed? What were their size? Speed?
Implement a 2 I/P and gate using Tran gates?
What is the difference between cmos and bipolar technologies?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
