Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1379You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1278What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1005For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
979Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1119Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1072For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
1178Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
1031Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
1131
Give the cross-sectional diagram of the cmos.
What are the steps required to solve setup and hold violations in vlsi?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Describe the various effects of scaling?
What types of high speed CMOS circuits have you designed?
Insights of a 4bit adder/Sub Circuit?
What are the steps involved in preventing the metastability?
What does it mean “the channel is pinched off”?
what is the use of defpararm?
For CMOS logic, give the various techniques you know to minimize power consumption
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
what is multiplexer?
Explain the Charge Sharing problem while sampling data from a Bus?
What are the Advantages and disadvantages of Mealy and Moore?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
