VLSI Interview Questions
Questions Answers Views Company eMail

Draw a 6-T SRAM Cell and explain the Read and Write operations

Infosys,

1050

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

Infosys,

1396

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

Infosys,

1297

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

Infosys,

1032

Draw a CMOS Inverter. Explain its transfer characteristics

Infosys,

927

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

Infosys,

1002

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

Infosys,

997

For CMOS logic, give the various techniques you know to minimize power consumption

Infosys,

1110

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

Infosys,

1060

Draw the SRAM Write Circuitry

Infosys,

930

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

Infosys,

1143

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

Infosys,

1095

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

Infosys,

1207

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

Infosys,

1047

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

Infosys,

1157


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Un-Answered Questions { VLSI }

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

3156


How logical gates are controlled by boolean logic?

855


Tell me how MOSFET works.

2176


Mention what are the two types of procedural blocks in Verilog?

1015


What is Noise Margin? Explain the procedure to determine Noise Margin?

2233


What are the different design techniques required to create a layout for digital circuits?

826


If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

932


What was your role in the silicon evaluation/product ramp? What tools did you use?

3454


what is multiplexer?

897


Explain how MOSFET works?

3038


Explain Cross section of an NMOS transistor?

789


Cross section of a PMOS transistor?

4518


what is the difference between the TTL chips and CMOS chips?

837


why is the number of gate inputs to CMOS gates usually limited to four?

1068


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3643