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VLSI Interview Questions
Questions Answers Views Company eMail

Draw a 6-T SRAM Cell and explain the Read and Write operations

Infosys,

1234

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

Infosys,

1591

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

Infosys,

1505

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

Infosys,

1246

Draw a CMOS Inverter. Explain its transfer characteristics

Infosys,

1135

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

Infosys,

1173

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

Infosys,

1227

For CMOS logic, give the various techniques you know to minimize power consumption

Infosys,

1349

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

Infosys,

1209

Draw the SRAM Write Circuitry

Infosys,

1140

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

Infosys,

1411

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

Infosys,

1242

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

Infosys,

1394

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

Infosys,

1249

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

Infosys,

1401


Post New VLSI Questions

Un-Answered Questions { VLSI }

Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1152


Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

1242


What types of CMOS memories have you designed? What were their size? Speed?

4606


For CMOS logic, give the various techniques you know to minimize power consumption

1349


Explain Basic Stuff related to Perl?

992


Explain what is the use of defpararm?

1100


What does it mean “the channel is pinched off”?

1308


What are the steps involved in designing an optimal pad ring?

1124


What is the difference between cmos and bipolar technologies?

1087


What are the different classification of the timing control?

1052


What is the ideal input and output resistance of a current source?

2953


Draw the Layout of an Inverter?

2444


what is SCR (Silicon Controlled Rectifier)?

1002


Explain how Verilog is different to normal programming language?

1184


Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1059