Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1396You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1297What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1032How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
1002For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
997Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1143Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1095For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
1207Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
1047Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
1157
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?
How logical gates are controlled by boolean logic?
Tell me how MOSFET works.
Mention what are the two types of procedural blocks in Verilog?
What is Noise Margin? Explain the procedure to determine Noise Margin?
What are the different design techniques required to create a layout for digital circuits?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
What was your role in the silicon evaluation/product ramp? What tools did you use?
what is multiplexer?
Explain how MOSFET works?
Explain Cross section of an NMOS transistor?
Cross section of a PMOS transistor?
what is the difference between the TTL chips and CMOS chips?
why is the number of gate inputs to CMOS gates usually limited to four?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
