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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1656You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1569What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1332How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
1204For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
1275Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1477Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1290For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
1449Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
1301Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
1449
What are the steps required to solve setup and hold violations in vlsi?
Explain various adders and difference between them?
What types of CMOS memories have you designed? What were their size? Speed?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
What types of high speed CMOS circuits have you designed?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
What is the function of tie-high and tie-low cells?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Explain the working of 4-bit Up/down Counter?
6-T XOR gate?
Explain the three regions of operation of a mosfet.
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Draw the SRAM Write Circuitry
What are the various regions of operation of mosfet? How are those regions used?
