Explain the operation considering a two processor computer system with a cache for each processor.
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
why is the number of gate inputs to CMOS gates usually limited to four?
Explain what is Verilog?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
Explain about 6-T XOR gate?
What was your role in the silicon evaluation or product ramp? What tools did you use?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
What happens if we delay the enabling of Clock signal?
Write a program to explain the comparator?
Basic Stuff related to Perl?
How can you model a SRAM at RTL Level?
Explain Cross section of an NMOS transistor?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
How does Vbe and Ic change with temperature?
