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VLSI Interview Questions
Questions Answers Views Company eMail

what is conductance and valence band?

1 6485

What is Fermi level?

5 10713

How does Vbe and Ic change with temperature?

Qualcomm,

3463

If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?

1 4534

what is Channel length modulation?

Intel,

2 7127

what is the doping?

5 8508

How does a pn junction works?

Wipro,

2 7565

What is the depletion region?

1 5601

Tell me the parameters as many as possible you know that used to character an amplifier?

1 3522

What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).

Analog Devices,

4 14726

What is the build-in potential?

Wipro,

1 3215

Tell me how MOSFET works.

2368

For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

2 11723

How does a Bandgap Voltage reference work?

3841

What is the ideal input and output resistance of a current source?

2950


Post New VLSI Questions

Un-Answered Questions { VLSI }

What is the difference between cmos and bipolar technologies?

1087


Mention what are the two types of procedural blocks in Verilog?

1214


How can you construct both PMOS and NMOS on a single substrate?

4930


What types of CMOS memories have you designed? What were their size? Speed?

3091


what is multiplexer?

1097


What are the different design techniques required to create a layout for digital circuits?

994


How does a Bandgap Voltage reference work?

3841


What was your role in the silicon evaluation or product ramp? What tools did you use?

2258


In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1126


For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

1193


What is the difference between the mealy and moore state machine?

1035


What are the various regions of operation of mosfet? How are those regions used?

1077


Explain how Verilog is different to normal programming language?

1179


What happens if we delay the enabling of Clock signal?

2299


Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

5217