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VLSI Interview Questions
Questions Answers Views Company eMail

Why is Extraction performed?

Intel,

1 7890

What is LVS, DRC?

IBM, Intel,

10 61332

Who provides the DRC rules?

Intel,

5 12034

What is validation?

Intel,

2 14144

What is Cross Talk?

Intel,

4 12552

Different ways of implementing a comparator?

Intel,

1 6469

What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

Intel,

4 8649

What is clock feed through?

Intel,

2 17467

Implement an Inverter using a single transistor?

Intel,

4 13274

What is Fowler-Nordheim Tunneling?

Intel,

2 8183

Insights of a Tri-state inverter?

Intel,

1 5441

If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

Intel,

2500

Differences between Array and Booth Multipliers?

Intel,

4075

Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

Intel,

3 18588

Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

Intel,

13 37410


Post New VLSI Questions

Un-Answered Questions { VLSI }

Working of a 2-stage OPAMP?

3183


What is the main function of metastability in vsdl?

1065


What is the function of tie-high and tie-low cells?

1085


Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

1368


Differences between Array and Booth Multipliers?

4075


For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

2393


Explain what is the use of defpararm?

1148


What are the different design constraints occur in the synthesis phase?

1101


How to improve these parameters? (Cascode topology, use long channel transistors)

2182


Implement a 2 I/P and gate using Tran gates?

4007


Draw the SRAM Write Circuitry

1186


why is the number of gate inputs to CMOS gates usually limited to four?

1337


Explain the working of 4-bit Up/down Counter?

4433


Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1105


Explain Cross section of an NMOS transistor?

1028