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What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
4 8464Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
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Tell me how MOSFET works.
What is the main function of metastability in vsdl?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
For CMOS logic, give the various techniques you know to minimize power consumption
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Explain what is the depletion region?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Explain how binary number can give a signal or convert into a digital signal?
Are you familiar with the term MESI?
Explain various adders and difference between them?
What does it mean “the channel is pinched off”?
What happens if we delay the enabling of Clock signal?
How about voltage source?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
