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What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
4 8838Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
13 37818
What are the different ways in which antenna violation can be prevented?
What is threshold voltage?
Mention what are the two types of procedural blocks in Verilog?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Design an 8 is to 3 encoder using 4 is to encoder?
Explain the operation of a 6T-SRAM cell?
What are the steps involved in designing an optimal pad ring?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Are you familiar with the term snooping?
Describe the various effects of scaling?
Draw a 6-T SRAM Cell and explain the Read and Write operations
Explain why present VLSI circuits use MOSFETs instead of BJTs?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
What transistor level design tools are you proficient with? What types of designs were they used on?
