What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
4 8649Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
13 37410
Working of a 2-stage OPAMP?
What is the main function of metastability in vsdl?
What is the function of tie-high and tie-low cells?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Differences between Array and Booth Multipliers?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Explain what is the use of defpararm?
What are the different design constraints occur in the synthesis phase?
How to improve these parameters? (Cascode topology, use long channel transistors)
Implement a 2 I/P and gate using Tran gates?
Draw the SRAM Write Circuitry
why is the number of gate inputs to CMOS gates usually limited to four?
Explain the working of 4-bit Up/down Counter?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Explain Cross section of an NMOS transistor?