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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
3310What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
1 5072Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
3180What transistor level design tools are you proficient with? What types of designs were they used on?
5107If not into production, how far did you follow the design and why did not you see it into production?
1 5344
Explain the working of Insights of an inverter ?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Explain why present VLSI circuits use MOSFETs instead of BJTs?
What is the ideal input and output resistance of a current source?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
What products have you designed which have entered high volume production?
Draw a 6-T SRAM Cell and explain the Read and Write operations
How does Vbe and Ic change with temperature?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
Implement a 2 I/P and gate using Tran gates?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What is the critical path in a SRAM?
