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VLSI Interview Questions
Questions Answers Views Company eMail

What is the difference between = and == in C?

Intel,

5 11216

Are you familiar with VHDL and/or Verilog?

Intel,

17 27521

What types of CMOS memories have you designed? What were their size? Speed?

Intel, Wipro,

4605

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

Intel,

3209

What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

Intel,

1 4926

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

Intel,

3077

What types of high speed CMOS circuits have you designed?

Infosys, Intel,

2 14453

What transistor level design tools are you proficient with? What types of designs were they used on?

Intel,

5027

What products have you designed which have entered high volume production?

Intel,

1 7353

What was your role in the silicon evaluation/product ramp? What tools did you use?

Intel,

3653

If not into production, how far did you follow the design and why did not you see it into production?

Intel,

1 5186

What is the most complicated/valuable program you written in C/C++?

HCL, IBM, Intel, TCS, TVS, Wipro,

23 42071

What is the difference between fifo and the memory?

DewSoft, Intel, Pentagon Rugged Systems,

6 29800

WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?

Intel, Wipro,

5 26520

Write a VLSI program that implements a toll booth controller?

Patni,

3939

Post New VLSI Questions

Un-Answered Questions { VLSI }

Explain various adders and difference between them?

1157

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1158

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1543

Explain what is the depletion region?

1030

Explain what is the use of defpararm?

1100

What transistor level design tools are you proficient with? What types of designs were they used on?

3392

what is verilog?

1058

What are the changes that are provided to meet design power targets?

1052

What are the different ways in which antenna violation can be prevented?

1070

For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

1196

Working of a 2-stage OPAMP?

3120

Explain what is multiplexer?

1030

What is the function of enhancement mode transistor?

1065

What is the purpose of having depletion mode device?

990

Explain about 6-T XOR gate?

1180

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