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VLSI Interview Questions
Questions Answers Views Company eMail

6-T XOR gate?

Intel,

4240

Differences between blocking and Non-blocking statements in Verilog?

Intel,

5 20995

Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

IIT, Intel,

1 20797

Differences between functions and Procedures in VHDL?

Intel,

5 54939

What is component binding?

Intel,

2 6280

What is polymorphism? (C++)

Intel,

2 6057

What is hot electron effect?

Intel,

3 13339

Define threshold voltage?

College School Exams Tests, Intel, JHG, Wipro,

32 135016

Factors affecting Power Consumption on a chip?

Intel,

7 17306

Explain Clock Skew?

Intel, nvidia,

6 21568

Why do we use a Clock tree?

Intel,

3 13392

Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

Intel,

2 8172

Explain the Various steps in Synthesis?

Intel,

3273

Explain ASIC Design Flow?

Intel, JK Associates, Mind Tree,

2 15397

Explain Custom Design Flow?

Intel,

2 7067


Post New VLSI Questions

Un-Answered Questions { VLSI }

Cross section of a PMOS transistor?

4769


what is the use of defpararm?

1142


How to improve these parameters? (Cascode topology, use long channel transistors)

2182


Explain the working of Insights of an inverter ?

1258


Draw the stick diagram of a NOR gate. Optimize it

1283


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1569


What is the function of tie-high and tie-low cells?

1085


Explain why present VLSI circuits use MOSFETs instead of BJTs?

1143


What happens if we delay the enabling of Clock signal?

2363


In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

1014


Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

1656


Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1125


What are the Factors affecting Power Consumption on a chip?

1286


Draw a 6-T SRAM Cell and explain the Read and Write operations

1287


Explain the working of 4-bit Up/down Counter?

4433