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Mention what are the different gates where Boolean logic are applicable?
Draw the stick diagram of a NOR gate. Optimize it
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
What are the main issues associated with multiprocessor caches and how might you solve them?
What is the function of tie-high and tie-low cells?
what are three regions of operation of MOSFET and how are they used?
How about voltage source?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain various adders and difference between them?
What is Noise Margin? Explain the procedure to determine Noise Margin?
Explain what is multiplexer?
What's the price in 1K quantity?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
