Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What is Body Effect?
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
How about voltage source?
What are the different design techniques required to create a layout for digital circuits?
What is look up table in vlsi?
Explain various adders and difference between them?
Are you familiar with the term MESI?
Explain what is the use of defpararm?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Explain the Various steps in Synthesis?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
