Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1059

In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1132

Mention what are three regions of operation of mosfet and how are they used?

1025

How does a Bandgap Voltage reference work?

3847

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

1593

Design an 8 is to 3 encoder using 4 is to encoder?

1292

Implement a 2 I/P and gate using Tran gates?

3972

Explain why is the number of gate inputs to cmos gates usually limited to four?

1456

Tell me how MOSFET works.

2373

Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1152

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1544

What is the critical path in a SRAM?

3114

What does the above code synthesize to?

2525

Draw a 6-T SRAM Cell and explain the Read and Write operations

1234

What transistor level design tools are you proficient with? What types of designs were they used on?

3392