VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

Explain the difference between write through and write back cache.

Intel,

2 16745

Are you familiar with the term MESI?

Intel,

2832

Are you familiar with the term snooping?

Intel,

3608

Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

Intel, Sun Microsystems,

2887

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

Intel,

1 5648

You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

Intel,

2721

Are you familiar with VHDL and/or Verilog?

Intel,

1 4487

What types of CMOS memories have you designed? What were their size? Speed?

e-tec, Intel,

3190

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

Intel,

2934

What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

Intel,

2492

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

Intel,

2376

What types of high speed CMOS circuits have you designed?

Intel,

2615

What transistor level design tools are you proficient with? What types of designs were they used on?

Intel,

3501

What products have you designed which have entered high volume production?

Intel,

2486

What was your role in the silicon evaluation or product ramp? What tools did you use?

Intel,

2382

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Un-Answered Questions { VLSI }

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3925

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

1713

What's the price in 1K quantity?

2882

Draw a 6-T SRAM Cell and explain the Read and Write operations

1336

What is the ideal input and output resistance of a current source?

3061

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1246

Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3846

Explain how Verilog is different to normal programming language?

1364

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

4171

How does Vbe and Ic change with temperature?

3568

Explain what is Verilog?

1155

What is the difference between cmos and bipolar technologies?

1181

Explain what is multiplexer?

1128

Explain various adders and difference between them?

1264

What is Noise Margin? Explain the procedure to determine Noise Margin?

2509

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