Answer / puli

latch up is the condition in which parasitic elements
establish a low impedance path between vdd and vss resulting
undesirable effects.



use guard rings or use well,substrate taps to prevent the
latch up

Answer / pawan hegde

1.GUARD RING , 2.Appropriate TAPS, 3.MAINTAIN WELL
PROXIMITY , 4 .Use Triple Well process , 5.Dual well
process 6 ???

Tell me the parameters as many as possible you know that used to character an amplifier?

1 Answers  

---

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

---

Explain sizing of the inverter?

0 Answers   Infosys,

---

What happens if we delay the enabling of Clock signal?

4 Answers  

---

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

---

Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

0 Answers   Intel, Sun Microsystems,

---

Explain the difference between write through and write back cache.

2 Answers   Intel,

---

What is Fermi level?

5 Answers  

---

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

---

Why is Extraction performed?

1 Answers   Intel,

---

Basic Stuff related to Perl?

0 Answers   Intel,

---

How about voltage source?

0 Answers  

---