Answer / puli

latch up is the condition in which parasitic elements
establish a low impedance path between vdd and vss resulting
undesirable effects.



use guard rings or use well,substrate taps to prevent the
latch up

Answer / pawan hegde

1.GUARD RING , 2.Appropriate TAPS, 3.MAINTAIN WELL
PROXIMITY , 4 .Use Triple Well process , 5.Dual well
process 6 ???

What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

---

What happens when the gate oxide is very thin?

3 Answers   Intel,

---

If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1 Answers   Intel,

---

What are the different classification of the timing control?

0 Answers  

---

Explain the Various steps in Synthesis?

0 Answers   Intel,

---

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

---

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

---

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

---

Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

---

What is SPICE?

4 Answers   Intel,

---

Factors affecting Power Consumption on a chip?

7 Answers   Intel,

---

If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

---