VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

Intel,

1 6846

Why is OOPS called OOPS? (C++)

ARM, Intel,

1 5409

What is a linked list? Explain the 2 fields in a linked list?

Intel,

1 8151

Implement a 2 I/P and gate using Tran gates?

Intel,

3972

Insights of a 4bit adder/Sub Circuit?

Intel,

3295

For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

Intel,

5 13852

Explain various adders and diff between them?

Intel,

1 5418

Explain the working of 4-bit Up/down Counter?

Intel,

4397

A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

Intel,

3 9723

Advantages and disadvantages of Mealy and Moore?

Intel,

2 40537

Id vs. Vds Characteristics of NMOS and PMOS transistors?

Brillient, Intel, ISRO,

1 17072

Explain the operation of a 6T-SRAM cell?

Intel,

4472

Differences between DRAM and SRAM?

Infosys, Intel, University, Wipro,

14 72263

Implement a function with both ratioed and domino logic and merits and demerits of each logic?

Intel,

3735

Given a circuit and asked to tell the output voltages of that circuit?

Intel, Omega Healthcare,

1 5026

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Un-Answered Questions { VLSI }

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1544

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

1153

Are you familiar with the term MESI?

2640

What are the steps involved in designing an optimal pad ring?

1125

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

2276

What are the steps required to solve setup and hold violations in vlsi?

1035

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3213

What are the different gates where boolean logic are applicable?

998

Why does the present vlsi circuits use mosfets instead of bjts?

1231

Differences between IRSIM and SPICE?

5394

Tell me how MOSFET works.

2373

Differences between Array and Booth Multipliers?

4017

Explain what is slack?

1021

How does a Bandgap Voltage reference work?

3847

What is the function of enhancement mode transistor?

1066

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