VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

Intel,

1 7007

Why is OOPS called OOPS? (C++)

ARM, Intel,

1 5567

What is a linked list? Explain the 2 fields in a linked list?

Intel,

1 8410

Implement a 2 I/P and gate using Tran gates?

Intel,

4062

Insights of a 4bit adder/Sub Circuit?

Intel,

3417

For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

Intel,

5 14318

Explain various adders and diff between them?

Intel,

1 5580

Explain the working of 4-bit Up/down Counter?

Intel,

4488

A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

Intel,

3 10006

Advantages and disadvantages of Mealy and Moore?

Intel,

2 40828

Id vs. Vds Characteristics of NMOS and PMOS transistors?

Brillient, Intel, ISRO,

1 17277

Explain the operation of a 6T-SRAM cell?

Intel,

4570

Differences between DRAM and SRAM?

Infosys, Intel, University, Wipro,

14 73243

Implement a function with both ratioed and domino logic and merits and demerits of each logic?

Intel,

3846

Given a circuit and asked to tell the output voltages of that circuit?

Intel, Omega Healthcare,

1 5193

Post New VLSI Questions

Un-Answered Questions { VLSI }

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1645

Differences between Array and Booth Multipliers?

4135

Explain what is scr (silicon controlled rectifier)?

1106

what is the difference between the TTL chips and CMOS chips?

1166

Working of a 2-stage OPAMP?

3236

Draw the stick diagram of a NOR gate. Optimize it

1331

Explain what is multiplexer?

1128

Explain the working of Insights of a pass gate ?

1303

Draw a CMOS Inverter. Explain its transfer characteristics

1231

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1253

Explain about 6-T XOR gate?

1364

What types of CMOS memories have you designed? What were their size? Speed?

4702

Explain how logical gates are controlled by Boolean logic?

1236

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

1316

Explain why is the number of gate inputs to cmos gates usually limited to four?

1550

For More Un-Answered { VLSI } Questions Click Here