Answer / rams

D latch is a device it simply transfers data from input to
output when the enable is activated.its used for the
forming of d flip flops.

Answer / sghsg

library ieee;
use ieee.std_logic_1164.all;

entity D_latch is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end D_latch;

architecture arch_D_latch of D_latch is
begin
process(d,clk)
begin
-- +ve level sensitive
if(clk = '1') then
q <= d;
else
q <= q;
end if;
end process;
end arch_D_latch;

Answer / bhushan

D-Latch is a level sensitive flip-flop.
output changes as long as clock is High(for +ve level
sensitive) or High(for -ve level sensitive)


library ieee;
use ieee.std_logic_1164.all;

entity D_latch is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end D_latch;

architecture arch_D_latch of D_latch is
begin
process(d,clk)
begin
-- +ve level sensitive
if(clk = '1') then
q <= d;
else
q <= q;
end if;
end process;

end arch_D_latch;

Describe the various effects of scaling?

0 Answers   Infosys,

---

Explain Cross section of an NMOS transistor?

0 Answers   Intel,

---

Explain various adders and diff between them?

1 Answers   Intel,

---

What is the difference between nmos and pmos technologies?

0 Answers  

---

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

---

What products have you designed which have entered high volume production?

1 Answers   Intel,

---

What is the difference between cmos and bipolar technologies?

0 Answers  

---

What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,

---

How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

---

Insights of a 2 input NAND gate. Explain the working?

1 Answers   Intel,

---

What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  

---

Give the expression for CMOS switching power dissipation?

2 Answers   Cypress Semiconductor,

---