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Differences between D-Latch and D flip-flop?
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Answer / abc
Answer 2 is wrong. latch can have a clock. Answer 1 is correct.
elaborating on it: difference is that for a latch the output
can follow input(like a buffer) if latch is in "pass" state,
else if the clock input is such that the its in "latch"
state then output is preserved. Whereas, flip-flop output
only changes at the clock edge(rising or falling depending
upon type of flop)
| Is This Answer Correct ? | 120 Yes | 24 No |
Answer / sarita bhan
Answer 3 is right. One more difference is that fllipflops
take twice the number of gates as latches
2) so automatically delay is more for flipflops
3)power consumption is also more.
| Is This Answer Correct ? | 78 Yes | 17 No |
Answer / chandrasheka kakanur
Latches are Level sensitive and the input values are
assigned only at the levels and latches does not require
less power consumtion than flip flops. Flip flops are edge
sensitive, as per assignment of clock the values are
assigned at a particular edge.
| Is This Answer Correct ? | 55 Yes | 14 No |
Answer / naeem khan
the difference between latche and flip flop is that , that
latchs used the level clock trigger while the flip flop
used the edge trigger clock.so this the is main difference
between the latchs and flip flop.
| Is This Answer Correct ? | 44 Yes | 14 No |
Answer / k.n.n.sarma
LATCH-LEVEL SENSITIVE
IT CONSISTS OF BOTH ENABLE AND CLOCK
FLIP FLOP-EDGE TRIGGERED
IT CONSISTS OF ONLY CLOCK AND NO ENABLE IS PRESENT FOR FLIP
FLOP.
| Is This Answer Correct ? | 38 Yes | 19 No |
Answer / harsh agrawal
In electronics, a latch is a kind of bistable multivibrator,
an electronic circuit which has two stable states and
thereby can store one bit of information. Today the word is
mainly used for simple transparent storage elements, while
slightly more advanced non-transparent (or clocked) devices
are described as flip-flops. Informally, as this distinction
is quite new, the two words are sometimes used interchangeably.
| Is This Answer Correct ? | 26 Yes | 10 No |
Answer / alekhya
latches are used as temperory buffers where as fliflops
used as registers
| Is This Answer Correct ? | 14 Yes | 0 No |
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Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;
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