Interested to Buy Any Domain ? << Click Here >> for more details...
Implement D flip-flop with a couple of latches? Write a VHDL
Code for a D flip-flop?
- 6 Answers
- 20248 Views
- Intel, I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
Answer / muthu
ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
entity gh_DFF is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end gh_DFF;
architecture a of gh_DFF is
begin
process(CLK,rst)
begin
if (rst = '1') then
Q <= '0';
elsif (rising_edge(CLK)) then
Q <= D;
end if;
end process;
end a;
| Is This Answer Correct ? | 36 Yes | 2 No |
Answer / balaji
library ieee;
use ieee.std_logic_1164.all;
entity d_ff is
port(d,clk:in std_logic;
q,q'bar:out std_logic);
end d_ff;
architecture a_d_ff of d_ff is
begin
process(clk)
begin
if rising_edge(clk) then
q<=d;
q'bar<=not d;
end if;
end process;
end a_d_ff;
| Is This Answer Correct ? | 32 Yes | 13 No |
Answer / seetharamukg
D flip-flop can be implemented by using 2 D-Latches.
---------- -----------
--|Din Q |-----|Din Q|---output of Flop
| D-latch1| | D-latch2 |
| ^ | | ^ |
----|----- ----|------
Clk -------------not-----
| Is This Answer Correct ? | 21 Yes | 12 No |
Answer / harvir
ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
entity gh_DFF is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end gh_DFF;
architecture a of gh_DFF is
begin
process(CLK,rst)
begin
if (rst = '1') then
Q <= '0';
elsif (rising_edge(CLK)) then
Q <= D;
end if;
end process;
end a;
| Is This Answer Correct ? | 12 Yes | 3 No |
Answer / hps
ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
entity gh_DFF is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end gh_DFF;
architecture a of gh_DFF is
begin
process(CLK,rst)
begin
if (rst = '1') then
Q <= '0';
elsif (rising_edge(CLK)) then
Q <= D; // The latch should_not be included
// ie:- instead of D ; D should used
end if;
end process;
end a;
| Is This Answer Correct ? | 5 Yes | 0 No |
Answer / rakesh
ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DFlip_Flop is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end DFlip_Flop;
Architecture of DFlip_Flop is
begin
---ANother way of writing code for creating D_Flip_Flop in VHDL
process(Clk, Rst)
begin
if (Rst ='1') then
Q <= '0';
elsif(clk='1' and clk'event) then
Q <= D;
end if;
end process;
end ;
| Is This Answer Correct ? | 0 Yes | 0 No |
What is the difference between nmos and pmos technologies?
Are you familiar with the term snooping?
What is the difference between the mealy and moore state machine?
Are you familiar with the term MESI?
Tell me how MOSFET works.
A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
Insights of a 4bit adder/Sub Circuit?
Cross section of a PMOS transistor?
What is component binding?
Explain Custom Design Flow?
Describe the various effects of scaling?
What's the price in 1K quantity?
86 Family 
