Answer / salla nagaraju

To implement $F=overline{(AB+CD)}$ in CMOS, the pull-down network (NMOS) has two parallel branches: one with NMOS A and B in series and another with NMOS C and D in series.The pull-up network (PMOS) is the dual: two series branches, each branch having PMOS A||B and PMOS C||D in parallel.This ensures that when $AB+CD=1$, NMOS pulls output low, and when $AB+CD=0$, PMOS pulls output high.Thus, the complementary network gives the required logic with proper CMOS operation.

While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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What does the above code synthesize to?

0 Answers   Intel,

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What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?

6 Answers   Intel,

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Implement an Inverter using a single transistor?

4 Answers   Intel,

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Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

2 Answers   Intel,

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Why does the present vlsi circuits use mosfets instead of bjts?

0 Answers  

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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Explain various adders and diff between them?

1 Answers   Intel,

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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