What is the difference between nmos and pmos technologies?

0 Answers  

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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Describe the various effects of scaling?

0 Answers   Infosys,

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Differences between netlist of HSPICE and Spectre?

1 Answers   Intel,

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How many bit combinations are there in a byte?

6 Answers   Intel,

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Implement F = AB+C using CMOS gates?

2 Answers   Intel,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

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Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

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What is the function of tie-high and tie-low cells?

0 Answers  

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