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VLSI Interview Questions
Questions Answers Views Company eMail

Explain CMOS Inverter transfer characteristics?

ADS,

3924

Explain sizing of the inverter?

Infosys,

4427

How do you size NMOS and PMOS transistors to increase the threshold voltage?

4 29559

What is Noise Margin? Explain the procedure to determine Noise Margin?

2458

Give the expression for CMOS switching power dissipation?

Cypress Semiconductor,

2 8325

What is Body Effect?

CG CoreEL, Cisco, TA,

2521

What happens to delay if you increase load capacitance?

Google,

1 3657

What are the limitations in increasing the power supply to reduce delay?

Infosys,

2 13514

How does Resistance of the metal lines vary with increasing thickness and increasing length?

Infosys,

3 13609

What happens if we increase the number of contacts or via from one metal layer to the next?

Infosys,

1 7571

Give the various techniques you know to minimize power consumption?

5 13088

Explain the Charge Sharing problem while sampling data from a Bus?

1 4666

What happens if we use an Inverter instead of the Differential Sense Amplifier?

3003

What is the critical path in a SRAM?

3197

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

Infosys,

4127


Post New VLSI Questions

Un-Answered Questions { VLSI }

What is the difference between the mealy and moore state machine?

1121


what is the difference between the TTL chips and CMOS chips?

1133


Explain Basic Stuff related to Perl?

1045


Explain why present VLSI circuits use MOSFETs instead of BJTs?

1155


Working of a 2-stage OPAMP?

3187


For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

2401


How do you size NMOS and PMOS transistors to increase the threshold voltage?

3035


Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

5273


For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

1257


Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1204


What is the purpose of having depletion mode device?

1053


You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

2676


For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1458


What are the steps involved in preventing the metastability?

1126


How does Vbe and Ic change with temperature?

3518