Answer / guest

Setup time: Time before the active clock edge of the
flipflop, the input should be stable. If the signal changes
state during this interval, the output of that flipflop
cann't be predictable (called metastable).

Hold Time: The after the active clock edge of the flipflop,
the input should be stable. If the signal changes during
this interval, the output of that flipflop cann't be
predictable (called metastable).

Answer / arpan

Setup time is the min time before the active edge of the
clock that the data gets stable. If the setup time is
violated then the logic enters into a metastable state. We
can say that setup time is violated when the logic is too
slow compare to clock. So, whenever we do simulations we do
setup time calculation in worst case. Since, in worst case
data changes too late. So, if the design passes the worst
case setup time, then its proper.
Hold time is the min time after the active edge of the clock
that the data should remain stable. Logic will also enter
into the metastable state if hold time is violated. We can
say hold violation occurs when the logic is too fast. So,
whenever we do simulation for hold time calculation we do in
best case since in best case data is changed too early. So,
if the design passes best case hold time, then its proper.

Answer / raghavendra

the setup and hold time constraints are
1.constraint for setup time:the data and clock should be available at the same time
2.constraint for hold time:the data should not change after clock tick.

they signify the correctness of the signal

Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,

---

Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

0 Answers  

---

In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

---

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

---

Are you familiar with the term snooping?

0 Answers   Intel,

---

What are the different measures that are required to achieve the design for better yield?

0 Answers  

---

What is polymorphism? (C++)

2 Answers   Intel,

---

Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

2 Answers   Intel,

---

Explain the working of differential sense amplifier?

1 Answers  

---

What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

---

Insights of a 2 input NAND gate. Explain the working?

1 Answers   Intel,

---

what is charge sharing?

0 Answers   Intel,

---