Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
Answers were Sorted based on User's Feedback
Answer / adi
Insert a small buffer to increase the skew between the two
regs. This can be quick fix only in some cases though
Is This Answer Correct ? | 13 Yes | 0 No |
Answer / pavankumar v vijapur
use register retiming concept .......
i.e split up comb delay in two paths using a flop
Is This Answer Correct ? | 4 Yes | 1 No |
Answer / ram
when there is a combo delay which is more than the clock
time period, though all the above can be a solution if the
delay is small, normally they mark it as a multi clock cycle
path.
Is This Answer Correct ? | 3 Yes | 1 No |
Answer / guest
Ideally, clock period will be increased (reducing maximum
operation frequency)
Is This Answer Correct ? | 3 Yes | 3 No |
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Explain the various Capacitances associated with a transistor and which one of them is the most prominent?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
What are the main issues associated with multiprocessor caches and how might you solve them?
Draw a 6-T SRAM Cell and explain the Read and Write operations
Draw the Layout of an Inverter?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
what is conductance and valence band?
WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?
what is SCR (Silicon Controlled Rectifier)?
How can you model a SRAM at RTL Level?
What products have you designed which have entered high volume production?