Answer / sarojini

static ram is a volatile memory. so it is easy to model a
sram at rtl level

What?s the difference between Testing & Verification?

6 Answers   Infosys,

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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

0 Answers   Infosys,

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Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

2 Answers   Intel,

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Why is OOPS called OOPS? (C++)

1 Answers   ARM, Intel,

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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what is Latch up?How to avoid Latch up?

3 Answers  

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Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?

6 Answers   Intel,

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers   Infosys,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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How to improve these parameters? (Cascode topology, use long channel transistors)

0 Answers  

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