Answer / sharekhan

Clock tree is usd for equal distribution of clock in a VLSI
circuitry.In this technique the VLSI blocks are at equal
distance from the central clock.This technique is ues to
eliminate skew problem.

Arrangemnet is in the form of alphabhet "H" with VLSI
blocks are arranged at the end of the alphabhet H and clock
circuitry aplied at the centre of the "H".THus each block
is at equal distance from the clock circuitry.

Answer / arghya sasmal

During CTS our goal is to
1) minimize the clock skew
2)minimize the clock tree power dissipation
In CTS buffers and inverters are placed in clock net to minimize the skew.

Clock nets are optimized and their driving cells are supposed to match RC values and impedance ...and minimize the clock tree power dissipation

Answer / purna

The main goals of CTS are
1. Clock signal is propagate to all flops in same time.
2. Low global and local skew.
3. Less insertion delay.
4. For low power designs Clock gating cells are added based
on the designer requirement.
5.Selecting a tree structure from (H,Y,binary and fish bone
etc...)
6. less number of buffer and inverters in the clock path.
7. Clock pin has high fanout to balance skew, we need to
synthesis the clock path separately.

In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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2 Answers   Cosmic Circuits, HP,

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2 Answers  

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