Differences between Signals and Variables in VHDL? If the
same code is written using Signals and Variables what does
it synthesize to?
Answer / seetharamukg
Signals updates a value after some "delta" time or at the
end of the process. But variable updates a value immediately.
Both variable and signals are synthesizable.
Designer should know hoe to use these 2 objects.
Ex: Signal usage
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_sig;
architecture SIG_ARCH of xor_sig is
signal D: STD_LOGIC;
begin
SIG:process (A,B,C)
begin
D <= A; -- ignored !!
X <= C xor D;
D <= B; -- overrides !!
Y <= C xor D;
end process;
end SIG_ARCH;
Variable usage:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity xor_var is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_var;
architecture VAR_ARCH of xor_var is
begin
VAR:process (A,B,C)
variable D: STD_LOGIC;
begin
D := A;
X <= C xor D;
D := B;
Y <= C xor D;
end process;
end VAR_ARCH;
Is This Answer Correct ? | 48 Yes | 9 No |
what is short Channel effect.
How logical gates are controlled by boolean logic?
What is a linked list? Explain the 2 fields in a linked list?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What is the function of tie-high and tie-low cells?
What is polymorphism? (C++)
How can you construct both PMOS and NMOS on a single substrate?
Insights of a 2 input NOR gate. Explain the working?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Explain the difference between write through and write back cache.
What's the price in 1K quantity?
Explain Custom Design Flow?