Explain ASIC Design Flow?
- 2 Answers
- 14310 Views
- Intel, JK Associates, Mind Tree, I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
Answer / amar
ASIC design flow:
Stands for Application specific integrated circuit.
This kind of design flow has been completely automated
with few manual steps
Below is the flow
1 ] system level specification
2 ]RTL coding and simulation
2 ] netlist synthesis , dft scan insertion ---> DFT ATPG,
STA,GLS can be run in this stage
3 ] physical design process
netlist extraction with actual parasitics
sign off STA , GLS , Power analysis will be done here
GDS2 ----> Manufacturer
In ASIC , We use standard cells which are predesigned and
pre verified cells created as library from where physical
design tools will choose the correct cell to place and route.
Comapre and contrast this with Custom IC design where we do
not have so much automation , and also we do not use
standard cells instead custom cells are created for use in
custom IC design
| Is This Answer Correct ? | 18 Yes | 2 No |
Answer / david schkolnik
To Answer #1 I must add the check done between steps:
After:
architecture is defined: Review with peers:
RTL coding: Logic simulation with tools like NCsim
Synthesis: first shot STA of (with estimated delays).
Formal verification against RTL (w/Formality)
DFT insertion and ATPG: Logic simulation, coverage, - Formal verification against
pre-DFT netlist.
Place and Route: sign-off STA (with actual delays)
LVS, DRC
Because the Verification process of the original code continues in parallel during the rest of the project, some bugs come up very late when it's too late to re-do the whole thing. Sometimes timing problems need late fixes. These small changes are called ECO, which are made straight on Layout. Then LVS needs to be run again and the result be analyzed by the top engineers in the team. Still, many bugs are born in this stage.
| Is This Answer Correct ? | 2 Yes | 2 No |
Insights of a Tri-state inverter?
Explain the working of Insights of an inverter ?
What types of high speed CMOS circuits have you designed?
What is the difference between nmos and pmos technologies?
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
How logical gates are controlled by boolean logic?
Are you familiar with the term snooping?
Who provides the DRC rules?
How about voltage source?
What happens to delay if you increase load capacitance?
Explain how binary number can give a signal or convert into a digital signal?
86 Family 
