Answer / sham

w r t VHDL component binding is binding of an entity with an architecture declared else where..

Answer / khush

If an entity contains many architectures and any one of
the possible architecture binding with its entity is done
using configuration. It is used to bind the architecture
body to its entity and a component with an entity.

Syntax:

configuration configuration_name of entity_name is
block_configuration;
end configuration_name.

Block_configuration defines the binding of components in a
block. This can be written as

for block_name
component_binding;
end for;
block_name is the name of the architecture body. Component
binding binds the components of the block to entities. This
can be written as,

for component_labels:component_name
block_configuration;
end for;

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