VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

How can you construct both PMOS and NMOS on a single substrate?

IBM, Intel,

4982

What happens when the gate oxide is very thin?

Intel,

3 14111

What is setup time and hold time?

Intel,

1 6318

Write a pseudo code for sorting the numbers in an array?

Intel,

2 14843

What is pipelining and how can we increase throughput using pipelining?

Intel,

1 5207

Explain about stuck at fault models, scan design, BIST and IDDQ testing?

Intel,

3 13355

What is SPICE?

Intel,

4 17709

Differences between IRSIM and SPICE?

Intel,

5434

Differences between netlist of HSPICE and Spectre?

Intel,

1 8987

What is FPGA?

Intel,

7 14897

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

Intel,

3378

Draw the Layout of an Inverter?

Intel,

2505

If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

Intel,

1 7030

Implement F = AB+C using CMOS gates?

Intel,

2 11473

Working of a 2-stage OPAMP?

Intel, Tata Elxsi,

3183

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Un-Answered Questions { VLSI }

Explain what is the depletion region?

1079

What are the different gates where boolean logic are applicable?

1061

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

1301

What are the main issues associated with multiprocessor caches and how might you solve them?

2221

What are the ways to Optimize the Performance of a Difference Amplifier?

2442

Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1105

What are the Advantages and disadvantages of Mealy and Moore?

1268

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

3378

What is the purpose of having depletion mode device?

1040

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1599

What is threshold voltage?

1182

What transistor level design tools are you proficient with? What types of designs were they used on?

3443

Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3783

Explain Cross section of an NMOS transistor?

1028

Draw the Layout of an Inverter?

2505

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