In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1129

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3823

Explain the three regions of operation of a mosfet.

1038

what are three regions of operation of MOSFET and how are they used?

1187

Explain what is scr (silicon controlled rectifier)?

1019

What does the above code synthesize to?

2524

Explain what is Verilog?

1053

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

3332

Differences between Array and Booth Multipliers?

4016

Draw a 6-T SRAM Cell and explain the Read and Write operations

1234

What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

2391

Draw the SRAM Write Circuitry

1140

Mention what are three regions of operation of mosfet and how are they used?

1023

Draw a CMOS Inverter. Explain its transfer characteristics

1135

Explain sizing of the inverter?

4374