Differences between blocking and Non-blocking statements in
Verilog?
Answers were Sorted based on User's Feedback
Answer / amit malik
cp mistake in 1st one.
-----------------------------------
Blocking statements are executed on after another
represented by '='
Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end
Ans
A = 1
B = 1
Non Blocking
instructions are executed concurrently
represented by '<='
Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A <= B;
B <= A;
end
Ans
A = 1
B = 0
| Is This Answer Correct ? | 66 Yes | 1 No |
Answer / appu
@ Remya,
With non-blocking statements as shown above, A will always
get the OLD/previous value of B, and B will always get the
OLD/previous value of A.
Because, in a non-blocking statement assignment, the right
hand side of the statement gets evaluated right away, but
doesn't get assigned to the left hand side of the statement
until at the end of the time step.
| Is This Answer Correct ? | 20 Yes | 1 No |
Answer / amit malik
Blocking statements are executed on after another
represented by '='
Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end
Ans
A = 1
B = 1
Non Blocking
instructions are executed concurrently
represented by '=>'
Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end
Ans
A = 1
B = 0
| Is This Answer Correct ? | 35 Yes | 18 No |
Answer / darshan
DURING BLOCKING STATEMENTS, PREVIOUS VALUES GETS STORED TO
THE LHS.
WHERE AS IN NON BLOCKING STATEMENT, SINCE IT IS EXECUTING IN
PARALLEL 1ST SIMULATOR READS AND STORES IN TEMPORARY
REGISTER INTERNALLY IN SIMULATOR. THEN AT THE END OF THE
TIME UNIT IT IS ASSIGNED TO THE LHS.
ANYWAYS FROM MY POINT OF VIEW A OR B DONT GET THE PREV/OLD
VALUE
| Is This Answer Correct ? | 7 Yes | 2 No |
Answer / remya
Yes,the explanation is ok but after a particular time
units,the value of B must be equal to 1 no?
| Is This Answer Correct ? | 6 Yes | 9 No |
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
How can you model a SRAM at RTL Level?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
What is hot electron effect?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Explain what is Verilog?
Explain the operation of a 6T-SRAM cell?
Draw the Layout of an Inverter?
Tell me the parameters as many as possible you know that used to character an amplifier?
What is LVS, DRC?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?