Are you familiar with VHDL and/or Verilog?

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Question Posted / markus

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Intel, I also Faced
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Are you familiar with VHDL and/or Verilog?..

Answer / vijayakunar

Very high speed integrated circut hardware discription
language.

Is This Answer Correct ?

53 Yes

6 No

Are you familiar with VHDL and/or Verilog?..

Answer / jp

Verilog is Hardware Description Language
VHDL : Very (High Speed Integrated Circuit) Hardware
Description Language

Is This Answer Correct ?

51 Yes

4 No

Are you familiar with VHDL and/or Verilog?..

Answer / veeramuthu k

yes

Is This Answer Correct ?

42 Yes

8 No

Are you familiar with VHDL and/or Verilog?..

Answer / muthu

yes

Is This Answer Correct ?

30 Yes

8 No

Are you familiar with VHDL and/or Verilog?..

Answer / guest

yes

Is This Answer Correct ?

19 Yes

8 No

Are you familiar with VHDL and/or Verilog?..

Answer / a.vidhya

Two industry standard hardware description languages, VHDL
and Verilog.macro and mega cells written in either VHDL or
Verilog.VHDL is a multitude of language or user defined
data types.Compared to VHDL, Verilog data types a re very
simple.VHDL allows concurrent procedure calls; Verilog does
not allow concurrent task calls.

Is This Answer Correct ?

8 Yes

1 No

Are you familiar with VHDL and/or Verilog?..

Answer / zameer

ya...vhdl is very high speep integrated circuit hardware
description language and verilog is verify logic hardware
description lang.

Is This Answer Correct ?

4 Yes

0 No

Are you familiar with VHDL and/or Verilog?..

Answer / radha

Im familiar with verilog

Is This Answer Correct ?

6 Yes

4 No

Are you familiar with VHDL and/or Verilog?..

Answer / suresh

VHDL for Very high speed hardware description language
VERILOG stands for verification logics.

Is This Answer Correct ?

3 Yes

2 No

Are you familiar with VHDL and/or Verilog?..

Answer / ipsita

vhdl

Is This Answer Correct ?

1 Yes

0 No

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Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

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