What types of CMOS memories have you designed? What were
their size? Speed?
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What's the price in 1K quantity?
How does Resistance of the metal lines vary with increasing thickness and increasing length?
What is LVS, DRC?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
How to find the read failiure probablity in SRAM?
How to improve these parameters? (Cascode topology, use long channel transistors)
What is clock feed through?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is Noise Margin? Explain the procedure to determine Noise Margin?
4 Answers Amkor, Cisco, Infosys, Intel,
What?s the critical path in a SRAM?
2 Answers Infosys, Intel, Texas,
Draw a 6-T SRAM Cell and explain the Read and Write operations