What types of CMOS memories have you designed? What were
their size? Speed?
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How does Resistance of the metal lines vary with increasing thickness and increasing length?
Explain the operation of a 6T-SRAM cell?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
Explain Clock Skew?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
Explain why is the number of gate inputs to cmos gates usually limited to four?
What is hot electron effect?
what is the doping?
Explain what is the use of defpararm?
What are the different types of skews used in vlsi?
Mention what are the different gates where Boolean logic are applicable?
What is the difference between fifo and the memory?
6 Answers DewSoft, Intel, Pentagon Rugged Systems,