Answer Posted / radha

Im familiar with verilog

How can you model a SRAM at RTL Level?

5361

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Give the cross-sectional diagram of the cmos.

660

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

784

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Explain how Verilog is different to normal programming language?

777

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

839

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6-T XOR gate?

3888

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Mention what are three regions of operation of mosfet and how are they used?

679

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Describe the various effects of scaling?

4410

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Draw the Layout of an Inverter?

2138

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Draw a 6-T SRAM Cell and explain the Read and Write operations

903

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

840

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

821

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1157

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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

2125

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What are the various regions of operation of mosfet? How are those regions used?

694

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