Explain how Verilog is different to normal programming language?

0 Answers  

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What are the different classification of the timing control?

0 Answers  

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what is body effect?

1 Answers  

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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Mention what are the different gates where Boolean logic are applicable?

0 Answers  

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

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What are the different ways in which antenna violation can be prevented?

0 Answers  

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Explain the Various steps in Synthesis?

0 Answers   Intel,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

0 Answers   Infosys,

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Are you familiar with the term MESI?

0 Answers   Intel,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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