In a SRAM layout, which metal layers would you prefer for
Word Lines and Bit Lines? Why?
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If not into production, how far did you follow the design and why did not you see it into production?
what are three regions of operation of MOSFET and how are they used?
What are the Factors affecting Power Consumption on a chip?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is a D-latch? Write the VHDL Code for it?
Insights of a 2 input NAND gate. Explain the working?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
Mention what are the two types of procedural blocks in Verilog?
What are the steps required to solve setup and hold violations in vlsi?
How can you model a SRAM at RTL Level?
Explain sizing of the inverter?
For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?