What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Cross section of a PMOS transistor?
what is multiplexer?
How does Vbe and Ic change with temperature?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What are the steps involved in designing an optimal pad ring?
What happens if we delay the enabling of Clock signal?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is Body Effect?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
How can you construct both PMOS and NMOS on a single substrate?
Explain the Charge Sharing problem while sampling data from a Bus?
