Answer / ramesh

0.18u has a higher cutoff lesser the Length better the
frequency

Answer / kamelesh

Ans:50hz

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers   Infosys,

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What types of high speed CMOS circuits have you designed?

2 Answers   Infosys, Intel,

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Have you studied buses? What types?

5 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Explain the working of Insights of a pass gate ?

0 Answers   Intel,

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Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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Why is Extraction performed?

1 Answers   Intel,

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Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,

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Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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what is charge sharing?

0 Answers   Intel,

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