How does a pn junction works?
- 2 Answers
- 6625 Views
- Wipro, I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
when we give forward bias, pn junction conducts the
currentfrom -ve to +ve.at reverse bias, it doesn't work.
| Is This Answer Correct ? | 5 Yes | 2 No |
When a P-type material and an N-type material are put together, The electrons from N side go to P side and holes from P side go to N side forming a depletion region at the junction. This junction develops a voltage which is dependent on the doping concentration. Now, the free electrons on N-Side require more energy to cross the depletion region. A +Ve voltage applied across the diode(Also called forward bias) can supply this energy.
When a -Ve voltage is applied, it will result in free carriers being pulled away from the depletion region thereby increasing its width. Hence, it will allow the current to pass only in one direction(i.e. when a +ve voltage is applied).
| Is This Answer Correct ? | 1 Yes | 0 No |
What is FPGA?
If not into production, how far did you follow the design and why did not you see it into production?
What is Fowler-Nordheim Tunneling?
What are set up time & hold time constraints? What do they signify?
What is Fermi level?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What happens if we delay the enabling of Clock signal?
What is the difference between = and == in C?
What is validation?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What are the different limitations in increasing the power supply to reduce delay?
What are the different gates where boolean logic are applicable?
86 Family 
