Answer / arjun_r

Input resistance - Must be very high(ideally infinite)
Output resistance - Must be very low(ideally zero)
Open Loop gain - Ideally Infinite
Input offset voltage - Ideally Zero
Output voltage range - Ideally Infinite
Slew Rate - desired to be high - High SR means the output is more sensitive to input
CMRR - Preferred High (Common mode gain should be low)

What is look up table in vlsi?

0 Answers  

---

Basic Stuff related to Perl?

0 Answers   Intel,

---

Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  

---

A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

3 Answers   Intel,

---

What is component binding?

2 Answers   Intel,

---

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

---

Explain what is scr (silicon controlled rectifier)?

0 Answers  

---

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

---

What types of high speed CMOS circuits have you designed?

0 Answers   Intel,

---

What are the steps involved in preventing the metastability?

0 Answers  

---

What does it mean “the channel is pinched off”?

0 Answers  

---

What is setup time and hold time?

1 Answers   Intel,

---