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Are you familiar with the term MESI?
If not into production, how far did you follow the design and why did not you see it into production?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Implement a 2 I/P and gate using Tran gates?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
How to improve these parameters? (Cascode topology, use long channel transistors)
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What are the different classification of the timing control?
What was your role in the silicon evaluation or product ramp? What tools did you use?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
What types of CMOS memories have you designed? What were their size? Speed?
Explain how logical gates are controlled by Boolean logic?
What products have you designed which have entered high volume production?
