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VLSI Interview Questions
Questions Answers Views Company eMail

What happens to delay if we include a resistance at the output of a CMOS circuit?

Infosys,

1 13427

Give the expression for calculating Delay in CMOS circuit?

Infosys,

1 7513

what is charge sharing?

Intel,

2307

Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

Infosys,

2 16059

Explain the working of differential sense amplifier?

1 6443

What happens if we use an Inverter instead of the Differential Sense Amplifier?

Infosys,

3267

What?s the critical path in a SRAM?

Infosys, Intel, Texas,

2 11508

What happens if we delay the enabling of Clock signal?

2301

What?s the difference between Testing & Verification?

Infosys,

6 30289

How can you model a SRAM at RTL Level?

Infosys,

5686

what is Latch up?How to avoid Latch up?

3 24539

What happens if we delay the enabling of Clock signal?

4 7077

Explain the Charge Sharing problem while sampling data from a Bus?

4659

Explain why & how a MOSFET works?

Infosys,

2 6968

Explain the various MOSFET Capacitances & their significance?

1 23310


Post New VLSI Questions

Un-Answered Questions { VLSI }

What transistor level design tools are you proficient with? What types of designs were they used on?

3392


Mention what are the two types of procedural blocks in Verilog?

1219


Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1152


what is the use of defpararm?

1102


What is the purpose of having depletion mode device?

991


Mention what are the different gates where Boolean logic are applicable?

1060


Explain the operation of a 6T-SRAM cell?

4472


How do you size NMOS and PMOS transistors to increase the threshold voltage?

2968


Draw the stick diagram of a NOR gate. Optimize it

1227


Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1543


What products have you designed which have entered high volume production?

2393


In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1129


Explain what is the use of defpararm?

1101


What is Body Effect?

2466


What happens if we use an Inverter instead of the Differential Sense Amplifier?

3267