What?s the critical path in a SRAM?
Answers were Sorted based on User's Feedback
Answer / arun
critical path occurs during reading operation
so ready delay = precharge delay + row deocder delay+
bitline discharge delay+ sense amplifier delay+ mux delay
| Is This Answer Correct ? | 8 Yes | 0 No |
Answer / mayank jansari
critical path is longest costing path in SRAM
| Is This Answer Correct ? | 0 Yes | 8 No |
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Explain the operation of a 6T-SRAM cell?
What are the steps involved in preventing the metastability?
How do you detect if two 8-bit signals are same?
What is the function of chain reordering?
While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?
6-T XOR gate?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Explain why is the number of gate inputs to cmos gates usually limited to four?
WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?
Explain the Working of a 2-stage OPAMP?
Mention what are three regions of operation of mosfet and how are they used?