What happens to delay if we include a resistance at the
output of a CMOS circuit?



What happens to delay if we include a resistance at the output of a CMOS circuit?..

Answer / madhu

delay increases

Is This Answer Correct ?    22 Yes 0 No

Post New Answer

More VLSI Interview Questions

What is the ideal input and output resistance of a current source?

0 Answers  


Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

0 Answers   Infosys,


Define threshold voltage?

32 Answers   College School Exams Tests, Intel, JHG, Wipro,


While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,


Draw the stick diagram of a NOR gate. Optimize it

0 Answers   Infosys,






Differences between functions and Procedures in VHDL?

5 Answers   Intel,


What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  


Have you studied buses? What types?

5 Answers   Intel,


Explain the various MOSFET Capacitances & their significance?

1 Answers  


What is validation?

2 Answers   Intel,


Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,


What is interrupt latency?

3 Answers  


Categories