What happens to delay if we include a resistance at the
output of a CMOS circuit?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Explain the three regions of operation of a mosfet.
Explain how Verilog is different to normal programming language?
What does it mean “the channel is pinched off”?
Are you familiar with VHDL and/or Verilog?
Why does the present vlsi circuits use mosfets instead of bjts?
What's the price in 1K quantity?
Differences between IRSIM and SPICE?
What is a D-latch? Write the VHDL Code for it?
What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What does the above code synthesize to?