Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same?
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Answer / jaya suriya
IN SPARTAN 3E BOARD.. THE INTERNAL CLOCK FREQUENCY IS
16MHZ... IF WE WANT TO INTERFACING THE EXT DIPLAY DEVICES
WE WON'T RUN IT WITH A NORMAL CLOCK FREQ(16
MHZ)....THATSWHY I HAVE TO CREATED NEW CLOCK PULSE WITH THE
FREQ OF 1HZ BY DEVIDING THE CLOCK..... TAKE THE NORMAL CLK
AS A REFERENCE...THIS IS KNOWN AS CLOCK DIVIDER CONCEPT...
ENTITY CLK_DIV IS
PORT(CLK: IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC);
END CLK_DIV
ARCH BEH OF CLK_DIV IS
VARIABLE COUNT:INTEGER:=0;
SIGNAL CLKN:STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT=8000000 THEN
NEWCLK<= NOT CLKN
COUNT:=0;
END PROCESS;
END BEH;
| Is This Answer Correct ? | 19 Yes | 13 No |
Answer / senthil
I am using the Mr.Suriya code with little modification.
ENTITY CLK_DIV IS
PORT(CLK: IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC);
END CLK_DIV
ARCH BEH OF CLK_DIV IS
VARIABLE COUNT:INTEGER:=0;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT=8000000 THEN
NEWCLK<= '1';
COUNT:=0;
ELSE
NEWCLK<= '0';
END IF;
END IF;
END PROCESS;
END BEH;
| Is This Answer Correct ? | 12 Yes | 12 No |
Answer / manju
please initialize the variables before using it in the
behaviour architecture or else it will be in the unknown
state still it has some legal value.
| Is This Answer Correct ? | 2 Yes | 4 No |
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Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;
86 Family 
