What is clock feed through?
- 2 Answers
- 16517 Views
- Intel, I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
Answer / sunil b r
he accumulation of a small positive charge on the source of
a MOS switch which occurs after the switch has been turned
off due to the parasitic capacitance that exists between the
gate and the source of the transistor, known as clock
feedthrough, is reduced by utilizing a split-gate MOS
transistor, and by continuously biasing one of the gates of
the split-gate transistor.
| Is This Answer Correct ? | 25 Yes | 3 No |
Answer / sudeep
Assume u have 2-3 partitions in ur design and now if the
clk for the second partition hs to go thru the first
partition, then the tool doesnt know which is the source or
root pin of the clk for the second partition, then u need
to specify the clock as a "feed thru" clock in the first
partition !
| Is This Answer Correct ? | 9 Yes | 15 No |
What is setup time and hold time?
What is component binding?
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?
Differences between netlist of HSPICE and Spectre?
How logical gates are controlled by boolean logic?
How can you model a SRAM at RTL Level?
Mention what are the two types of procedural blocks in Verilog?
What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
Write a VLSI program that implements a toll booth controller?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
what is Channel length modulation?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
86 Family 
