Answer / nikki

Post layout extraction is neccessary to get the accurate
netlist , with parasitic capacitance and rasistance. Post
layout simulation are done using the extracted neltist as
this gives a better approximation of what the circuit
behaviour would be in silicon.

For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

---

How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

---

In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

---

Explain what is Verilog?

0 Answers  

---

What happens when the gate oxide is very thin?

3 Answers   Intel,

---

What is the build-in potential?

1 Answers   Wipro,

---

What are the main issues associated with multiprocessor caches and how might you solve them?

1 Answers   Intel,

---

Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

---

Explain why & how a MOSFET works?

2 Answers   Infosys,

---

Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,

---

Explain the working of differential sense amplifier?

1 Answers  

---

What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

---