Answer / nikki

Post layout extraction is neccessary to get the accurate
netlist , with parasitic capacitance and rasistance. Post
layout simulation are done using the extracted neltist as
this gives a better approximation of what the circuit
behaviour would be in silicon.

What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

1 Answers   Intel,

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0 Answers   Intel,

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0 Answers   Intel, Wipro,

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Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

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5 Answers   Intel,

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2 Answers  

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0 Answers   Intel,

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0 Answers   Infosys,

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0 Answers  

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what is verilog?

0 Answers  

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Write a pseudo code for sorting the numbers in an array?

2 Answers   Intel,

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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