Answer / nikki

Post layout extraction is neccessary to get the accurate
netlist , with parasitic capacitance and rasistance. Post
layout simulation are done using the extracted neltist as
this gives a better approximation of what the circuit
behaviour would be in silicon.

Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

0 Answers   Intel,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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what is conductance and valence band?

1 Answers  

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What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

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Cross section of an NMOS transistor?

3 Answers   Intel,

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Are you familiar with the term MESI?

0 Answers   Intel,

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Are you familiar with the term snooping?

1 Answers   Intel,

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Explain what is the use of defpararm?

0 Answers  

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

4 Answers   Intel,

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