Answer / pradipta sarkar

tristate is a inverter with 3 o/p state: 1,0,z(high
inpedence state).it is implementated by adding two more nmos
(or pmos)-1 btwn d original nmos& o/p,1 btwn d pmos &o/p to
a odinary inverter. depending on wheather the additional 2
nmos are kept on/off d o/p behaves like normal inverter/z
respectively.

For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

2 Answers  

---

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

---

Tell me the parameters as many as possible you know that used to character an amplifier?

1 Answers  

---

What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,

---

How binary number can give a signal or convert into a digital signal?

0 Answers  

---

Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

---

Are you familiar with the term snooping?

1 Answers   Intel,

---

What are the different classification of the timing control?

0 Answers  

---

How can you model a SRAM at RTL Level?

1 Answers  

---

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

---

What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

---

What is the function of enhancement mode transistor?

0 Answers  

---