Answer / rajashekar @ nitt

give input at base and connect resistor at collector and
gnd at emitter,vcc at collector finaaly take output at
collector.

Answer / harshgandhi126

A single transistor itself is an inverter.Connect resistor
and +Vcc to collecot and Gnd to Emmiter. After that give an
input to Base terminal and take output between Collector
and Ground.

Answer / sharath & bhanu

Use a enhancement mode n-mos MOSFET and give i/p to base,
source to vdd and drain to o/p pin. Enhancement mode keeps
MOSFET always in ON state. Hence i/p logic '1' turns off
the transistor thus making o/p logic '0'

Answer / prateek

connect the gate of nmos to vdd so that it is always on
give the input at drain and tap the output from source.

What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?

1 Answers  

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

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What is threshold voltage?

0 Answers  

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Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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what is charge sharing?

0 Answers   Intel,

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0 Answers   Intel,

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1 Answers  

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1 Answers   Intel,

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Draw the Layout of an Inverter?

0 Answers   Intel,

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What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  

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