What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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What is latchup? Explain the methods used to prevent it?

2 Answers   Intel,

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What happens when the gate oxide is very thin?

3 Answers   Intel,

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What is the ideal input and output resistance of a current source?

0 Answers  

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

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What does it mean “the channel is pinched off”?

0 Answers  

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  

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Explain why & how a MOSFET works?

2 Answers   Infosys,

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