What products have you designed which have entered high
volume production?
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What was your role in the silicon evaluation/product ramp? What tools did you use?
What are the different classification of the timing control?
Working of a 2-stage OPAMP?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
why is the number of gate inputs to CMOS gates usually limited to four?
Explain what is the depletion region?
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Explain the difference between write through and write back cache.
What types of CMOS memories have you designed? What were their size? Speed?
Give various factors on which threshold voltage depends.
Differences between blocking and Non-blocking statements in Verilog?