What is the critical path in a SRAM?

0 Answers  

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Write a VLSI program that implements a toll booth controller?

0 Answers   Patni,

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Are you familiar with the term MESI?

1 Answers   Intel,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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Basic Stuff related to Perl?

0 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,

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What is the difference between = and == in C?

5 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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What are the various regions of operation of mosfet? How are those regions used?

0 Answers  

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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What is component binding?

2 Answers   Intel,

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